| ACC-No. |
Title of the Project Work |
Name of the student(s) |
Name of the Supervisor |
| T001 |
Implementation of Data Remapping for Object Oriented Languages |
Ayush Mittal |
Dr. M B Srinivas |
| T031 |
Design and Simulation of Fuzzy Logic Controller |
Keerthi, Lal Kale |
Prof Srinivas M B |
| T069 |
Towards realizing optimal reversible logic circuits |
Himanshu |
Dr. M B Srinivas |
| T122 |
Project report on a low powe 256 KB siam design |
Abhilesh & Rajnikant |
Dr. Rameshwar Rao |
| T123 |
Implementation of FHSS / FM transmitter for software defined radio |
Naga Sitaram M |
Dr. Rameshwar Rao |
| T124 |
DVB common scrambling algorithm using Verilog |
Naveen |
Dr. Rameshwar Rao |
| T128 |
Implementation of G 729 voice code |
Sandeep & Pandu |
Dr. Rameshwar Rao |
| T129 |
Implementation of Routing information protocol (RIP) |
Roop Rajesh & Ashish |
Dr. Rameshwar Rao |
| T130 |
802.11 wireless transmitter |
Umesh & Praveen |
Dr. Rameshwar Rao |
| T164 |
Design of USB-I(2) Bridge |
Venkateshwara rao, A M |
Dr. M Satyam |
| T165 |
Multichannel H264 Decoder Implementation on Hardware Accelerated Platform |
Md. Wajid |
Dr. M Satyam |
| T166 |
Multichannel H264 Decoder Implementation on Hardware Accelerated Platform |
Praveen, GVR |
Dr. M Satyam |
| T167 |
Embedded Voltage Regulator |
Umesh Khetan |
Dr. M Satyam |
| T168 |
Stub Series Terminated Logic (SSTL) for 1.5V and 1.8V |
Kranthi kumar, M |
Dr. M Satyam |
| T169 |
VC-1 Decoder for a Multi-Format Video Decoder
|
Swathi, Y |
Dr. M Satyam |
| T170 |
Project Report on Performance Analysis of Resource allocation Types in LTE |
Hari Rohit, V |
:
Dr. M Satyam |
| T172 |
Project Report on Design and analysis of Ultra Wideband LNA for 3.1 to 10.6 Ghz |
Ganesh B. Nalawade |
Dr. Syed Azeemuddin |
| T173 |
Project Report on Corekit Packaging for JPEG Core |
Abhishek Srivastava |
Dr. Syed Azeemuddin |
| T174 |
Solar Panel Maximum Power Point Tracking |
Pradeep kumar reddy, D |
Dr. M Satyam |
| T175 |
Solar Panel Maximum Power Point Tracking |
Rooprajesh R |
Dr. M Satyam |
| T176 |
Development of a VMM based Vweerification Environment for 10 Gigabit Ethernet MAC |
Sri Devi Polasanapaili |
Dr. M Satyam |
| T177 |
Development of a verification plan for PCI Express 3.0 VIP Using VMM Planner |
Arjun Shetty |
Dr. M Satyam |
| T178 |
Project Report on Verification Methodology for HSS Testsites |
Naveen Segu |
Dr. M Satyam |
| T179 |
Project Report on Maximum Power Point Tracking for PV System |
G. Konda Reddy |
Dr. M Satyam |
| T180 |
Project Report on Comparison of Test Compression Techniques in ASICs |
Shashank S B |
Dr. M Satyam |
| T181 |
Microcode-Based Memory BIST |
Narra Praveen Kumar |
Dr. M Satyam |
| T182 |
Development of a TLM Based Verification Environment for Display Block Design of an Oscilloscope |
Dolly Radha |
Dr. M Satyam |
| T183 |
Project Report on Comparison of Test Compression Techniques in ASICs |
Rajanikant Sakarlya |
Dr. M Satyam |
| T181 |
Design of a CMOS Chopper OP.AMP with Integrated Continuous time Low Pass Filter |
Rakesh Kumar Sahoo |
Prof Srinivas M B |
| T197 |
A Dissertation on Anchor Free Localization and Routing Strategies for Mobile and Static Wireless Sensor Networks |
Md. Aquil Mirza |
Dr. G. Ram Murthy |
| T217 |
Efficient and High-Speed FFT Architecture for Software Defined Radio |
Shashank Mittal |
Prof. M B Srinivas |
| T235 |
Sentence Realisation from ***-of Words with Dependency Constrains |
Karthik Kumar G |
Prof. Rajeev Sangal & Dr. Suresh Purni |
| T236 |
Transition Inversion Based for Power Coding for Buffered Bus System |
Abhinav |
Prof. Govindarajulu & Dr. Suresh Purini |
| T289 |
Modified Glitch-free and Cascadable Adiabatic Logic Circuits |
Prashanth Paramahans |
Prof. Satyam Mandavilli |
| T292 |
ESD and Over Voltage *** Issues in Modern IC Technology |
Akshay Kumar |
Prof. Satyam Mandavilli |
| T330 |
Implementation and Analysis of Low Power Methodologies using Dual Core RISC Processor |
Shivang Kaushik |
Prof M B Srinivas |
| T347 |
Testing of Programmable Logic Blocks in FPGA |
Rahul R Purohit |
Prof M Satyam |
| T348 |
Development of 802.11 Access Point Data Model Using Systemverilog |
Krishna, A V |
Prof M Satyam |
| T349 |
High Speed and Hardware Efficient ASIC Implementations of Advanced Encryption Standard |
Prashanth, Gade |
Prof M Satyam |
| T350 |
Study on Self Healing Circuits for Digital Applications |
Paritosh Bandari |
Prof M Satyam |
| T351 |
Digital Phase Locked Loop |
Phani Kumar, S |
Prof M Satyam |
| T352 |
CMOS Single cycle 64-bit Comparator |
Bhaskar Kakani |
Prof M Satyam |
| T353 |
16 Bit Sigma-Delta D/A Converter for Audio Applications |
Pradeep, K |
Prof M Satyam |
| T354 |
Interfacing Graphics LCD Controller with FPGA |
Malavika Sharma |
Prof M Satyam |
| T355 |
Mosfet Device Modeling |
Venkat Reddy, Uppala |
Prof M Satyam |
| T356 |
High Speed Parallel CRC based Signature Analyzer using Unfolding Pipelining and Retiming |
Mulluri Venugopalaram |
Prof M Satyam |
| T357 |
An Efficient Variable Length FFT Processor |
Vanam Suresh Kumar |
Prof M Satyam |
| T358 |
Study on the Design of the Phase Locked Loop |
Pavan Kumar, Gopalapuram |
Prof M Satyam |
| T359 |
Implementation of Retiming Techniques for Sequential Circuit Optimization |
Archana Rajagopalam |
Prof M Satyam |
| T360 |
An Efficient Out-of-Order Execution Unit for Multiple Instruction Sources with Shared Functional Units |
Aruna Kumar, P A |
Prof M Satyam |
| T361 |
Design and Development of Scheduling Algorithm for G Language Compilar |
Suman Chalana |
Prof M Satyam |
| T362 |
Implementation of Clock Cating Technique for FPU Block and Automating the process of Verification |
Chandra Babu Gowd K |
Prof M Satyam |
| T363 |
RTL Implementation of Input / Output Interface Core for Testing Communication Chips |
Mohammed Ameenuddin |
Prof M Satyam |
| T364 |
Implementation of EXTSS in Expander |
Sujatha R |
Prof M Satyam |
| T365 |
Low Voltage Low Current High Efficiency Power Supplies |
Vinidhra S |
Prof M Satyam |
| T366 |
Efficient Techniques for Reporting and tracking the errors in the Verification of NVIDIA’s Next Generation GPU at Full Chip Level |
Mahantesh K tondihal |
Prof M Satyam |
| T367 |
Functional Coverage Test for NAND Flash Controller |
Anu Mariam John |
Prof M Satyam |
| T368 |
ECO FLOW |
Shilpi Varshney |
Prof M Satyam |
| T369 |
Exploring Accelerators using High-Level Synthesis |
Milan Sadaria |
Dr Shubhajit Roy Choudhary |
| T370 |
Testing of BCU (Bus Control Unit) |
Sasi Kumar Baiju |
Prof M Satyam |
| T371 |
Design and Implementation of Test Plan for Coreaxitoahbl |
Maheswar Rao K |
Prof M Satyam |
| T372 |
Study of Performance Testing methodology for NVIDIA’s Next Generation GPUs and Exploration of Simulation Speedup Techniques |
Nagarjuna Udutha |
Prof M Satyam |
| T373 |
Simulation and Verification for the DDR Impedance Calibration |
Sai Krishna Kumar S |
Prof M Satyam |
| T374 |
Design and Testing of Serial Peripheral Interface |
Syed Mudassir Hassan |
Prof M Satyam |
| T377 |
Project Report on Low Power Linear Feedback Shift Register |
Kashif Hussain Ahmed |
Prof M Satyam |
| T510 |
Multi-Threaded Processor Analysis Process Design and FPGA Emulation |
Ankur Rajvanshi & Santosh Kumar P |
Prof M B Srinivas |
| T561 |
Unit Level Functional verification of PDM Transmitter DMIC Module using UVM |
Pradeep N |
Dr. Suresh Purini |
| T562 |
Design of Lottery based Arbiter Interfaced with AMBA-AXI Bus |
Hrishikesh Chillal |
Dr. Suresh Purini |
| T563 |
Power Analysis of Digital Circuits |
Shruti Chormalle |
Dr. Syed Azeemuddin |
| T564 |
Unit Level Verification of UART using UVM |
Arun Goutham, S |
Dr. Suresh Purini |
| T565 |
BLDC Motor Control Commutation algorithms for E-bike |
Vemula Naveen Kumar |
Dr. Syed Azeemuddin |
| T566 |
Functional Verification of Sensorless Field Oriented Control for PMSM on SOC |
Abhiram Sai Krishna, B |
Dr. Shubhajit Roy Choudhary |
| T567 |
Implementation of 32-Bit Risc Processor |
Abhimanyu Singh |
Dr. Syed Azeemuddin |
| T568 |
Characterization of IO and Clock Minimum Pulse Width in Smart Fusion2 |
Anudeep, K |
Dr. Suresh Purini |
| T569 |
Performance Benchmarking of C6678 Multicore DSP Processor for General Purpose HPC |
Samyak Gandhi |
Dr. Suresh Purini |
| T570 |
Modeling & Verification of MPIO Block in FPGAs |
Ruchin Jain |
Dr. Shubhajit Roy Choudhary |
| T571 |
Porting and Integration of Bullet Physics Simulation in to 3DGC Through GPU Using OpenGL |
Parveez Iqbal |
Dr. Syed Azeemuddin |
| T572 |
Hardware and Software Optimization of Block Ciphers and Implementation of Linear Cryptanalysis on Block Ciphers |
Venu Nalle |
Dr. Suresh Purini |
| T573 |
Enhancing Instruction-Fetch-Unit (IFU) Level Methodologies for Processor Verification |
Venkat Sai Hariprasad |
Dr. Suresh Purini |
| T574 |
Robust Railway Crack Detection Scheme (RRCDS) using LED-LDR Assembly |
Rashmi Soni |
Dr. Syed Azeemuddin |
| T575 |
Functional Simulation and Coverage Analysis SoC IP Interconnect Buses and Bridges |
Hiten Jayswal |
Dr. Suresh Purini |
| T576 |
Functional Modeling Ofcsi-3 Host and Sensor |
Rangateja, R |
Dr. Suresh Purini |
| T577 |
Design of Reconfigurable LNA |
Mansi Bhargava |
Dr. Syed Azeemuddin |
| T578 |
Testing and Detection of Failure Modes in Missile Interface Unit and On-Board Computer |
Phani Sriram |
Dr. Shubhajit Roy Choudhary |
| T579 |
Performance Evaluation of Texas Instruments C6678 Multicore DSP Processor for High Performance Computing Applications in Computational Fluid Dynamics |
Varun Sarma Velamuri |
Dr. Shubhajit Roy Choudhary |
| T580 |
Project Report on Performance Characterization of Cortex-M3 in Smartfusion2 |
Govardhan Golla |
Dr. Vijaya Sankara Rao, P |
| T581 |
Performance Comparison of Hardware Accelerators |
Sai Krishna Teja, K |
Dr. Suresh Purini |
| T582 |
A Project Report on High Speed Ser-Des Cores Power File Generation Flow & Accelerated Verification Model for HSS Analog Receiver |
Karthik Kumar, A |
Dr. Suresh Purini |
| T583 |
Complementing ATPG for Testing Thermal Sensor |
Sachin, Y |
Dr. Suresh Purini |
| T584 |
Verification of Lottery Based Arbiter Interfaced with AMBA-AXI Bus with UVM |
Nupoor Vyas |
Dr. Suresh Purini |
| T585 |
Implementation of APB Bus protocol, AHB-Lite Bus Protocol and UART Frame Processor in Verilog HDL |
Niranjan Reddy, A |
Dr. Shubhajit Roy Choudhary |
| T586 |
People Detection in Video Surveillance |
Saumya Suneja |
Dr. Suresh Purini |
| T587 |
Cyclic Combinational Circuits |
Praveen Kumar Verma |
Dr. Shubhajit Roy Choudhary |
| T783 |
Next Generation PCIe IP for SSD’s |
Yash Jajoo |
Dr Rahul Shrestha |
| T784 |
Virtual Prototyping System for Rapid Product Development |
Venkata Sravani Karnati |
Dr Rahul Shrestha |
| T785 |
LDO (Low Drop Out) Linear voltage Regulator Circuit Design in 14nm-FinFET Technology Node |
Bhaskar Ellaboina |
Dr Rahul Shrestha |
| T786 |
Verification of Serial Interface IPs |
Mandar A Mande |
Dr Rahul Shrestha |
| T787 |
Automation Tool for IP/VIP (PCIe, NVMe) Management |
Dushyant Duhan |
Dr Rahul Shrestha |
| T788 |
Analysis and Deep-Dive in Standard Cell Library Development Aspects: in advance technology nodes |
Utkarsh Garg |
Dr Rahul Shrestha |
| T789 |
UVM Based Testbench Architecture and Functional Coverage Verification for an Interconnect Babric |
Dewarkshi Knowar |
Dr Rahul Shrestha |
| T790 |
Area Efficient Matrix Multiplier |
Mohammad Aaquib Khan |
Dr Rahul Shrestha |
| T791 |
Single Source Methodology to have Specs, Design Execution, and Project Execution Status as Single |
Sonam Agarwal |
Dr Rahul Shrestha |
| T792 |
X-Tolerance, Test Coverage and Pattern Count Analysis of Design using IP-Based Scan DFT Architecture |
Shivangi Singhal |
Dr Rahul Shrestha |
| T793 |
Layer Traits Optimization Project at IBM |
Banu M Pranay |
Dr Rahul Shrestha |
| T794 |
Verification of Subset of USB Project at Qualcomm |
Syed Sameena Begum |
Dr Rahul Shrestha |
| T795 |
Optimization of Dictionary Generation Algorithm for Ziv-Lempel Compression |
Akshay Poshattiwar |
Dr Rahul Shrestha |
| T796 |
Design of an Input Buffer for Low Voltage Supply and High Frequency of Operation |
Harihara Sravan A |
Dr Rahul Shrestha |
